Finite Element Analysis of Flip Chip Packages

摘要

Rip-chip electronic package undergoes thermal loadings during its curing process and operation life. Due to the mismatch in coefficient of thermal expansion (CTE) of various components, the flip-chip assembly experiences various types of thermally induced stresses and strains, especially at the interface of the chip/underfill or underfill/substrate and also around the solder ball region. Experimental measurement of these stresses and strains is extremely tedious and rigorous due to the physical limitations in the dimensions of the flip-chip assembly. While experiments provide accurate assessment of stress/strain at certain locations, a parallel finite element (FE) studies can complementarity determine the displacement, strain and stress fields over the entire region of the flip-chip assembly. Such combination of the experimental and finite element studies is ideal to yield a successful stress analysis of the flip-chip assembly under the desired loading conditions. In this study finite element analysis has been conducted to determine the various stresses under thermal loading condition ranging from -40°C to 150°C. A two-dimensional finite element model of the assembly consisting of the silicon chip, underfill, solder ball and substrate has been developed. Stresses such as σ_(11), σ_(12), ε(12) etc. are extracted and analyzed for individual components, and the whole assembly. Detailed description on FE modeling is presented and the failure of flip the chip assembly is discussed.