SYSTEMS-LEVEL INTEGRATION FOR FOCUSED BEAM SCATTEROMETRY

摘要

The state of the art in optical lithography continues to push transistor critical dimensions below 15 nm, creating the need for extremely high-resolution metrology techniques as a result [1,2]. The International Technology Roadmap for Semiconductors has projected that the transistor logic half-pitch (critical dimension) reach 10 nm in industry by 2025 (See Table 1 below). Towards this end, the metrology of such fine features is a critical enabling technology. Ideally, the inspection of nanoscale features would be performed on an a priori basis; in reality, however, the features are well beyond the diffraction limit of the light used to inspect them, creating the need for more advanced strategies with longer inspection times.