A placement methodology for power optimizing macro block-based VLSI layouts is presented. This technique uses simulated annealing to target solutions with reduced switched capacitance. Its implementation is shown to be consistent and capable of producing competitive layouts whose quality is maintained when problem sizes are scaled up. The results obtained on a set of MCNC benchmarks indicate that power reductions over 16% are possible with increases of less than 1% in delay and total wirelength.
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