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Macro layout verification apparatus to detect error when connecting macro terminal in LSI design layout
Macro layout verification apparatus to detect error when connecting macro terminal in LSI design layout
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机译:宏布局验证装置,用于在以LSI设计布局连接宏终端时检测错误
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摘要
A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.
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