Highly efficient digital CMOS accelerator for image and graphics processing

摘要

This paper presents a novel high-bandwidth digital accelerator for image and graphics applications. The proposed architecture outperforms previously proposed processing in-memory architectures in speed, area and power by up to several orders of magnitude. Several variations of the design have been implemented in 2.5V 0.25μm and 8V 0.18μm CMOS technology.