COMBINING SOI TECHNOLOGY AND ASYNCHRONOUS DESIGN FOR POWER REDUCTION

摘要

Silicon on Insulator (SOI) technology & asynchronous design are both techniques advocated for low power systems. The paper describes a design that combines both approaches to provide a power efficient, high performance adder. The adder is a static 16-bit ripple carry design with a carry completion circuit. This exploits the data dependency inherent in many arithmetic operations enabling a small, simple adder design to offer an average performance, which is comparable to that from a more complex, synchronous adder consuming greater power. SOI technology offers a further saving in power principally due to being operated at lower supply voltages than compared with bulk CMOS for the same performance. Simulation results presented demonstrate that significant power saving can be achieved while maintaining speed by combining these two approaches.