STRAIN ANALYSIS OF DEEP SUB-MICRON CMOS DEVICES BY TEM/CBED IN THE <230> ZONE AXIS

摘要

In the last decade it has become evident that one of the major issues for the deep sub-micron integrated circuit technologies regarding yield, device performance and stability is the mechanical stress built up in the layers and the silicon substrate. Therefore the quantitative characterisation of these stresses is of increasing importance, what requires techniques with high spatial resolution for the stress determination in the substrate. The main scope is the correlation between this stress analysis and the device performance. Presently, the only experimental technique available, which allows one to determine the strain field distribution in sub-micron CMOS devices, without the need of a strain model, is the convergent beam electron diffraction (CBED) technique of the transmission electron microscopy. An alternative method based on electron diffraction contrast imaging has also been proposed; it requires the knowledge of a strain distribution, however.