A megapixel CMOS imager with charge binning

摘要

An active pixel sensor array (APS) with programmable resolution was realized in standard 0.5 μm CMOS technology. For operation under poor lighting conditions, the charge of sub-regions of 2 * 2 respectively 4 * 4 pixels can be summed, yielding a corresponding sensitivity enhancement. In that way the maximum resolution of 1024 * 1024 can be reduced to 512 * 512 or 256 * 256. Based on a charge skimming mechanism, the required circuitry can be implemented in any logic CMOS technology without process modifications. Output through 1, 2 or 4 analog channels clocked at a pixel rate up to 40 MHz each allows a frame rate up to 160 frames/sec at an overall power dissipation of 70 mW.