1.0-Volt, 9-bit Pipelined CMOS ADC

摘要

A 9-bit, 1.0-Vpipelined analog-to-digital converter has been designed using the switched-opamp technique. The input signal for the converter is brought in using a novel passive interface circuit. The design also features a low-voltage multiplying analog-to-digital converter (MDAC) and an improved common mode feedback circuit for a switched-opamp. The prototype chip implemented in a 0.5 μm CMOS technology has DNL and INL of 0. 6 and 0.9 LSB, respectively, and achieves 50.0 dB SNDR at 5 MHz clock rate. As the supply voltage is raised to 1.5 V the clock frequency can be increased to 14 MHz. The power consumption from a 1.0 V supply is 1.6 mW.