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Timing-driven detailed placement for standard-cells based on lookup-table delay model

机译:基于查找表延迟模型的标准单元的时序驱动的详细放置

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This paper presents a timing-driven detailed placement algorithm for standard-cell VLSIs based on a new lookup-table delay model. The new model can give more accurate delay estimation. We use local optimization in detailed placement and a net weighting method to cope with timing constraints. Timing verifications are carried out after each optimization iteration and net weights are adapted dynamically. We present 4 methods to modify net weights and study the combination effect of these methods. Experimental results show that our net-weighting method can reduce the maximum delay up to 15 percent compared to nontiming-driven placement, with little loss in the total wire length.
机译:本文基于新的查找表延迟模型介绍了标准单元VLSI的时序驱动的详细放置算法。新模型可以提供更准确的延迟估计。我们在详细放置和净权力方法中使用本地优化来应对时序约束。在每个优化迭代和净重动态调整后进行定时验证。我们提供了4种方法来修改净重并研究这些方法的组合效果。实验结果表明,与未定迁驱动的放置相比,我们的净加权方法可以将最大延迟降低到15%,总线长度少损失。

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