A timing-driven standard-cell placement method based on cell-clustering and the new placement model

摘要

In this paper, a new timing-driven cell placement method based on the new placement model is proposed for VLSI standard cell layout. The proposed method consists of two stages: global placement and detailed placement. In the first stage, the set of clusters are constructed by clustering cells, considering registers, for which the timing constraints are given. Then, with the simulated annealing based method, clusters are placed on the chip area, which is partitioned into the set of global bins. In the proposed method, the shape of each cluster is not restricted to a rectangle, but can be arbitrarily given under some conditions. This placement model is called the amoeba model. Since the flexibility of cluster placement is increased due to this new placement model, a satisfactory placement satisfying timing constraints can be obtained. In the second stage of the proposed method, each cluster is decomposed into the set of cells, and cells are assigned to cell rows, considering timing constraints, to produce a final cell placement.