Simultaneous Allocation and Floorplanning

摘要

As the feature size of VLSI circuit scales down, signal delay introduced by wire becomes the key factor dominating circuit's performance. Minimization of wire delay becomes oen of the most important subjects in VLSI design methodology research. This paper proposes a new algorithm that incorporates Slicing-Tree structure based floorplanning with the resource allocation in high-level synthesis, by partitioning scheduled data-flow-graph (DFG). Since both floorplanning and allocation can use the information generated from the other step, the algorithm is able to greatly optimize wire length. Experiments show its efficiency.