Are double edge-triggered designs the future of low-power synchronous digital circuits?

摘要

Clocking power has a large role to play in the overall power dissipation of synchronous circuits. In this paper, we investigate double edge-triggered (DET) designs as a new paradigm for low power synchronous digital circuits. Based on our investigation of existing semi-custom blocks we find that roughly 65 - 68percent of the Clocking power is due to the clock tree. Hence, the potential for reducing powr dissipation by reducing the clock frequency by half, is large. However, existing DET flip-flops do not realize the full benefits of this decrease in clock frequency. The reason for this lies in the implementation of existing DETs, which suffer from large Input and Vdd power dissipation (existing DET flip-flops consume double the current from the input and supply lines when compared to existing single edge-triggered (SET) flip-flops). These two constituents of Clocking power (Input and Vdd power) cannot be reduced by halving the clock frequency. Further, the paper identifies issues that need attention for the use of DET flip-flops in existing industrial designs.