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Optimum design method for synchronous digital circuits by forth and selective setting of tilting - circuits

机译:第四,倾斜电路的选择性设定的同步数字电路优化设计方法。

摘要

Optimal design method and apparatus for synchronous digital circuits by retiming through selective flipflop positioning and electronic circuit configuration produced by executing the method. The method is for designing a synchronous digital electronic circuit that comprises cells and clocked flipflops interconnected by nets and running at a predetermined clock period, operates as follows. First, uniform-directedly as starting from any cell for any sub-path emanating therefrom its associated delay is accumulated. Next, if for such sub-path the accumulation result exceeds a predetermined integer number of clock periods. The sub-path in question is signalled for subsequent provision with such integer number of flipflops and its accumulation is terminated. Finally, all elementary cell-to-cell connections are provided with flipflops in minimal accordance with said signalling. The invention is particularly advantageous with large circuits such as used in digital video processors and with small clock periods.
机译:通过选择性触发器定位和执行该方法所产生的电子电路配置的重定时进行同步数字电路的最佳设计方法和装置。该方法用于设计同步数字电子电路,其包括单元和通过网络互连并以预定时钟周期运行的时钟触发器,其操作如下。首先,对于从其开始产生的任何子路径,从其任何相关的延迟开始统一定向地累积。接下来,如果对于这种子路径,累加结果超过了预定的整数个时钟周期。发信号通知所讨论的子路径以随后提供具有这样整数数目的触发器,并且其累积被终止。最后,最小限度地根据所述信令向所有基本单元到单元连接提供触发器。本发明对于诸如用于数字视频处理器中的大型电路以及较小的时钟周期特别有利。

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