Synchronous digital electronic circuits and their design and operation

摘要

A method of designing a synchronous digital electronic circuit comprising clocked flip-flops and cells interconnected by a net and operating in a predetermined clock period is performed as follows. First, the associated delays accumulate in the same direction starting from any cell for any subpath exiting the cell. Next, for the subpath, if the accumulation result exceeds a predetermined number of clock periods, the accumulation ends by sending a signal for subsequent provision of the predetermined number of flip-flops to the subpath in question. Finally, a minimum of flip-flops are provided to all basic cell-to-cell connections in accordance with the signal transmission. The present invention is particularly advantageous for large circuits and small clock periods, such as those used in digital video processors.