Data-driven dynamic logic versus NP-CMOS logic, a comparison

摘要

Data-driven dynamic logic (D/sup 3/L) is an appropriate candidate for replacing conventional dynamic logic in many cases. In a previous paper, we have shown how a D/sup 3/L-based design can be used in place of a conventional domino logic (Rafati et al., ISCAS vol.1, pp.752-5, 2000). The designed circuit has been shown to have up to 30% less power dissipation compared to its domino counterpart. This is in addition to the fact that no speed degradation was found. In this paper, after a brief introduction on NP-CMOS logic and D/sup 3/L, we show how to convert an NP-CMOS design to a D/sup 3/L one. Then, the results of simulations performed on a 16-bit barrel shifter are demonstrated and compared for static, NP-CMOS and D/sup 3/L design styles.