Test support processors for enhanced testability of high performance circuits

摘要

A solution for testing fast-switching bidirectional signal lines using an array of technology-specific transceivers is described in [1]. This method uses an active component located between the device-under-test (DUT) and the automated testequipment (ATE) to reduce electrical interconnect delays to less than 150ps.In this paper, the transceiver array concept is extended to include higher-level test processes such as real-time algorithmic pattern generation (APG), multi-gigahertz signal multiplexing, and others. The active test component is therefore called a "TestSupport Processor" (TSP). It greatly reduces the functionality and performance capability required of the ATE, while maintaining signal integrity, and improving overall test quality.In its minimum configuration, the TSP provides an array of technology-specific transceivers very close to the DUT, as described in [1]. This reduces transmission line effects, allowing for at-speed test of fast I/O switching characteristics. Thistechnique may lead to lower-cost, higher-speed ATE by simplifying and standardizing the pin electronics.Beyond the minimum configuration, higher-level test processes may be included in the TSP, depending upon the DUT test requirements. The TSP is specifically intended to complement and support existing DFT and BIST structures within the DUT. In someapplications it may be possible to reduce BIST overhead by off-loading test functionality to the TSP, thereby reducing recurring silicon costs.The use of the TSP provides an additional degree of freedom for partitioning the test problem, and may result in a significant paradigm shift for future ATE architectures. The TSP represents an economic alternative to (projected)