Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment

摘要

SEMATECH has sponsored a "Test Method Evaluation" study to understand the trade-offs among the most common test methodologies used in the industry[1,2]. This paper presents the results of the failure analysis portion of that project. The testing,reliability stressing, characterization, fault diagnosis and physical analysis results are presented for 25 devices including "IDDq-only" failures and "delay test-only" failures.ATPG is about test functionality that leads to test patterns to determine the quality of a chip. Traditionally, this technology has been available at the gate level and this paper describes the need to move higher. High Level is defined as any level inthe abstraction chain that is above gates. DRC and DFT technology have already moved to higher levels of abstraction. If necessity is the mother of invention, High Level ATPG is not far behind because the need is there.