Using Karnaugh Maps in Software Requirements Analysis

摘要

Faulty requirements leading to design deficiencies have been shown to be an avoidable root cause of many product failures. Reflecting the theme of the 2017 International System Safety Society Conference, this paper is an effort to push the boundaries of system safety by proposing a novel approach for discovering faulty or missing software requirements by adapting a proven methodology heretofore used in circuit analysis. Karnaugh Mapping is employed in Application Specific Integrated Circuit (ASIC) design to minimize power consumption, facilitate temperature control, increase functionality, and minimize the number of physical logic gates. Karnaugh Maps (K-Maps) are ideally suited to impose order on logical requirements that describe the operation of electronic circuits. With the assumption that software requirements are expressible as logical statements, this paper assesses the ability of Karnaugh Mapping to effectively deconstruct and rationalize developmental requirements in the analysis of software, and seeks to demonstrate that K-Maps can be used not only to minimize the number of requirements but also to detect missing requirements. The analysis conducted in the course of developing this paper indicates that K-Maps can effectively identify faulty requirements in two examples of varying complexity providing that sematic conventions are established and observed.