FAULT INJECTION WITH SIMULATION IN VHDL MODELS AND ITS APPLICATION TO A SIMPLE MICROCOMPUTER SYSTEM

摘要

This paper presents the design of a tool for fault injection on VHDL models. The tool allows the user to inject faults at the logic, RTL and algorithmic level. It takes advantage of the descriptive power of the VHDL in different abstraction levels. The tool has been built over a VHDL simulator for IBM-PC platforms. It is easy to use, and it exhibits both versatility and portability advantages. With the purpose of proving the properties of the tool, a set of faults have been injected in a VHDL model of a simple 8-bit computer running a workload program. Faults of type stuck-at and stuck-open have been injected in the signals and variables of both the processor and memory models. The paper also presents the pathology of the propagated errors, measuring their latency and classifying them. This information can be used in the study of fault-detection and tolerance mechanisms.