Speeding up Power Estimation of Sequential Circuits by Circuit Compaction

摘要

Power estimation for CMOS sequential circuits is difficult because of sequential feedback loops embedded in the circuits. This paper presents a new method which combines the simulation method and probabilistic approach originally used in combinational circuits to complete power estimation of sequential circuits with improved accuracy andcomputation efficiency. Some speed up is obtained by compacting the circuit before simulation. Experimental results show that our method is a good complement to existing estimation techniques.