HSIM- An High Level Fault Simulation Algorithm and Simulator for Combinational Vlsl

摘要

In this paer, we present a novel high level fault simulator, HSIM, for high level combinational circuits. In HSIM, according to the need of simulation, the circuits are described in two hierarchical levels: the high level and the gate level. To simulate the faults belong to a part of a circuit system at the gate level, the rest of the system is not required to be described at the gate level. A gate level fault simulator is applied to simulate the stuck-at faults in the Module Under Simulation (MUS). At the high level, functional simulation technique is applied to simulate all the possible high level fault effects. Experimental results for seven benchmark circuits show that HSIM outperforms other gate level simulators. Moreover, HSIM has the good performance in simulating variou sizes of circuit systems. Experimental results of HSIM for different numbers of test patterns, are also presented.