EB Tester Fault Localization Algorithm for Combinational Circuits by Utilizing Fault Simulation and Test Pattern Sequence for EB Tester

摘要

An EB tester fault localization algorithm for combi- national circuits utilizing a fault list generated in concurrent fault simulation and test pattern sequence is proposed. In the algorithm, first, an initial fault candidate list and con- corrent fault lists on internal signal lines are obtained by performing concurrent fault simulation on a test pattern for which the LSI tester detected an error on one of the output pins. Then, using the concurrent fault lists, the signal line to be probed is chosen so that the fault candidate list is narrowed down maximally.