Test generation for VLSI digital circuits is in general case a complicated computational task, where the test patterns are derived in accordance to the level of cricuit modeling and the chosen fault model. The main area of interest is modeling the VLSI circuits at the functional and behavioral level of description, using RT (Register Transfer) languages and VHDL (VHSIC Hardware Description Language). TPG (Test Patterns Generation) algorithms are based on random methods, heuristics and deterministic methods. This paper is focused towards an investigation of the advantages and disadvantages of using genetic algorithms (GAs) for TPG process on RT and functional level. The TPG method using GAs at the functional and behavioral level of digital circuit modeling was proposed and first experiments showed the reason of another research and possibility to join it to the computational TPG methods.
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