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Synchronous bus arbitration with constant logic per module

机译:每个模块的恒定逻辑的同步总线仲裁

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A novel technique for distributed synchronous bus arbitration is presented. The proposed scheme is based on two orthogonal arbitration functions, one that employs bounded-weight binary codes, and another that employs unitary codes. This scheme trades off bus-width with arbitration-time and arbitration logic per device, such that both arbitration time and arbitration logic (per device) can be reduce by increasing bus width. Alternatively, this method allows the number of devices connected to a bus to be increased without changing the arbitration logic of each device (or the number of arbitration steps), only the width of the arbitration bus must be increased in this case.
机译:提出了一种用于分布式同步总线仲裁的新技术。该方案基于两个正交的仲裁职能,其中一个采用有界重量二进制代码,另一个采用统一代码。该方案对每个设备的仲裁时间和仲裁逻辑交易了总线宽度,从而通过增加总线宽度可以减少仲裁时间和仲裁逻辑(每个设备)。或者,该方法允许增加连接到总线的设备的数量而不改变每个设备的仲裁逻辑(或仲裁步骤的数量),在这种情况下,仅必须增加仲裁总线的宽度。

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