BUS CONTROL LOGIC OVERRIDES MEMORY ARBITRATION CONTROL LOGIC FOR DUAL BUS ARCHITECTURE COMPUTER

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• 3. ARBITRATION CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE [P] . MY112381A . 2001-06-30

  机译： 具有双总线架构的计算机系统的仲裁控制逻辑

• 4. A computer system having dual bus architecture with arbitration control logic [P] . IN181076B . 1998-04-18

  机译： 具有仲裁控制逻辑的双总线体系结构的计算机系统

• 5. ARBITRATION CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE [P] . SG42882A1 . 1997-10-17

  机译： 具有双总线架构的计算机系统的仲裁控制逻辑

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