Analysis of latch-effect in insulated gate bipolar transistors

摘要

Presents an analytical model of the latch-up effect in insulated gate bipolar transistors (IGBT). The model is based on an equation that describes the voltage distribution along the n/sup +/-p emitter junction of the parasitic thyristor. Expressions describing latch-up current I/sub LT/ and its dependence upon geometrical and electrophysical parameters of the devices with various topologies are derived. It is shown that I/sub LT//sup -1/ is proportional to the sheet resistance of the p-base of the parasitic thyristor and gain factor of the p-n-p transistor. I/sub LT/ decreases if under-gate region width and especially n/sup +/-emitter width increase. The derived formulas determine the temperature dependence of I/sub LT/. Obtained results are in good agreement with the available published data.