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A Novel 20-100μm Pitch IC-to-Package Interconnect and Assembly Process for Pb-free Solder, Copper or Gold Stud Bumps

机译:一种新的20-100μm间距IC-to-Packet互连和用于无铅焊料,铜或金螺柱凸块的组装工艺

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This paper presents a novel IC-to-package interconnect and assembly process for ultra fine pitch flip chip with Pb-free solders, copper, nickel or gold stud bumps and other low-standoff interconnects. Current flip-chip technology is capable of 130-150μm bump pitch and ITRS, iNEMI and other roadmaps identify the need for less than 50-100μm peripheral pitch flip-chip interconnections in the next few years. Several interconnect methods are being pursued as alternative to current lead-free solders due to concerns with interconnect fatigue reliability as the pitch decreases to 20μm. These include copper posts/pillars, nickel or other nano-structured interconnects, and gold stud bumps. For any of these interconnects, it is anticipated that an underfill material will be necessary to handle the CTE mismatch between the IC and the organic substrate. One of major challenges for ultra-fine pitch (20-100μm) flip-chip attach is the ability to dispense underfill effectively without voids and defects over large ICs with low stand-off height (10-40μm) interconnects. The need for highly filled low CTE and high modulus underfill materials to absorb strains in the ultra-fine pitch interconnects places additional demands on underfill processing. The innovative interconnect and assembly process presented here overcomes these challenges and also has the potential to solve the yield problems associated with current no-flow underfill processes. Initial process development was performed using lead-free solder interconnect and details of the assembly process, bonding conditions, and new underfill material will be discussed. Based on extensive process parameter optimization, defect-free interconnect assembly with underfill at 100μm pitch for a 20 mm×20 mm IC has been demonstrated with excellent solder wetting to the substrate pads. The novel approach in this paper is also applicable to copper, nickel, gold or other types of interconnects and enables the use of underfill materials with optimum combination of thermo-mechanical properties.
机译:本文介绍了一种新型的IC-to-Packet互连和组装工艺,用于超细俯仰倒装芯片,具有无铅焊料,铜,镍或金螺柱凸块和其他低间隔互连。电流倒装芯片技术能够为130-150μm凸起间距和ITRS,INEMI和其他路线图识别未来几年内不到50-100μm的外围间距倒装芯片互连。由于互连疲劳可靠性的担忧减小至20μm,正在追求几种互连方法作为当前无铅焊料的替代。这些包括铜柱/支柱,镍或其他纳米结构互连和金螺柱凸块。对于任何这些互连,预计将需要底部填充材料来处理IC和有机基材之间的CTE失配。超细沥青(20-100μm)倒装芯片附着的主要挑战之一是能够有效地分配底部填充物,没有空隙,并且在具有低脱扣高度(10-40μm)互连的大型IC上的缺陷。对于高度填充的低CTE和高模量底部填充材料的需求,以吸收超细间距互连中的菌株对底部填充处理的额外要求。这里提出的创新互连和装配过程克服了这些挑战,并且还有可能解决与当前无流量底部填充过程相关的产量问题。使用无铅焊料互连和组装过程的细节进行初始过程开发,将讨论粘合条件和新的底部填充材料。基于广泛的工艺参数优化,已经证明了20mm×20mm IC的100μm间距的底部填充物的无缺陷互连组件,并具有优异的焊料到基板焊盘。本文的新方法也适用于铜,镍,金或其他类型的互连,并能够使用底部填充材料,具有最佳的热机械性能组合。

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