Performance Analysis of Different Reduced Precision Redundancy based Full Adders

摘要

Many electronic devices may have manufacturing defects or internal failures which cause errors in the devices. These errors are called soft errors, which are hard to detect and remove. Reduced Precision Redundancy (RPR) is the most efficient technique to remove soft error with less area and power. In this technique, the RPR is combined with Triple Modular Redundancy (TMR) voter logic to remove soft errors with still lesser power and area overhead. There are different types of majority voter logic circuit designs which can be used in RPR based full adder design to remove soft errors. In this paper, different majority voter logic designs are surveyed and implemented in RPR based full adder. These RPR based full adders analyzed for area, power and delay. As per the analysis it is found that NOR gates based majority voter combined with RPR is having less area and NOR gates based majority voter combined with RPR is having the less power and the NAND gates based majority voter combined with RPR is having the less delay