首页> 外文会议>Electronics Packaging Technology Conference >Mid-Process Through Silicon Vias Technology using Tungsten Metallization: Process Optimazation and Electrical Results
【24h】

Mid-Process Through Silicon Vias Technology using Tungsten Metallization: Process Optimazation and Electrical Results

机译:使用钨金属化通过硅通孔技术中途进行中途:工艺优化和电气结果

获取原文

摘要

Through Silicon Via (TSV) is a one of the more important bricks for 3D stacking and offer different integration approaches. The via-last approach has been first introduced into production. Yet the via-first approach is also currently actively investigated since it has some advantages particularly the use of high conformal deposition materials for isolation and filling of the TSVs enabling higher density of connections or high voltage operations required for certain final product applications. We will show results on process development and integration of 70μm deep annular TSVs using tungsten as filling material on a dedicated test chip vehicle. First the complete process flow will be presented. Then, process development work and issues will be addressed. At first we will present developments on the annular trenches opening aiming at favorable slopes and minimum roughness. Deep RIE TSV etching process will be illustrated. For the isolation of the TSV a comparison between SACVD and DHDP deposition oxide will be then discussed. A special focus will be done on W filling sequence using multiple deposition and etch-back steps with different deposition process recipes and a final Chemical Mechanical Polishing (CMP) planarization of the TSVs. The backside process is also presented with the optimization of the back-lapping and CMP process to obtain a stress free silicon surface with no degradation of the TSVs as well as a minimum topology enabling a good back side contact. Backside interconnection is also presented featuring RDL (redistribution Layer) and die-to-wafer attach with bumps technology. Then electrical characterizations will be presented. A specific test vehicle was designed to study the TSV density and proximity impact with different number of rings and ring width TSV designs. Daisy chains, specific structures to measure TSV resistance similar to Kelvin structures, interdigitated chains to measure via leakage, and special structures to stress at very high voltage (up to 1000V), were designed. The electrical results from those specific structures will be discussed.
机译:通过硅通孔(TSV)是3D堆叠的更重要的砖块之一,并提供不同的集成方法。首先将普通的方法引入生产中。然而,目前还在主动研究了通孔第一方法,因为它具有一些优点,特别是使用高保形沉积材料来隔离和填充TSV,从而实现某些最终产品应用所需的更高密度或高压操作。我们将在专用测试芯片车辆上展示使用钨作为填充材料的过程开发和70μm深环TSV的结果。首先,将提出完整的过程流程。然后,将解决流程开发工作和问题。首先,我们将在旨在有利的斜坡和最小粗糙度上的环形沟槽上提出开发。将说明深rie tsv蚀刻过程。为了分离TSV,然后讨论SACVD和DHDP沉积氧化物之间的比较。使用具有不同沉积工艺配方的多个沉积和蚀刻步骤以及TSV的最终化学机械抛光(CMP)平坦化,将在W填充序列进行特殊焦点。还通过对后研磨和CMP工艺进行了后侧过程,以获得应力自由硅表面,没有劣化TSV的劣化以及使得能够良好的背面接触的最小拓扑。背面互连也呈现RDL(再分配层)和芯片晶圆,带有凸起技术。然后呈现电学特性。设计特定的测试车辆以研究与不同数量的环和环宽度TSV设计进行TSV密度和接近冲击。菊花链,特定结构测量TSV电阻类似于Kelvin结构,设计了通过泄漏的互化链条,并设计了以非常高的电压(高达1000V)应力的特殊结构。将讨论那些特定结构的电气结果。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号