Ferroelectric FET as a Low-Power Device with Reduced SCEs and RDF Effect

摘要

It is known that for a classical field-effect transistor (FET), the subthreshold swing (SS) cannot be reduced below the Boltzmann limit of 60 m V/dec. Recently, it has been proposed that by instilling a ferroelectric material in the gate stack the SS can be reduced below 60 mV/dec limit, which also defines the minimum limit of power dissipation. Simulations were carried out using Sentaurus TCAD for the Ferroelectric FET having Si doped HfO_2 as a ferroelectric material and SiO_2 as a linear dielectric in the gate stack and results show that SS is brought down below 60 mV/dec, with high I_(ON)/I_(OFF) ratio and low threshold voltage. Short-channel effect (SCE) and random dopant fluctuation (RDF) is also investigated for various channel length and channel doping concentration.