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0.228 μm2 trench cell technologies with bottle-shapedcapacitor for 1 Gbit DRAMs

机译:瓶形0.228μm 2 沟槽电池技术1 Gbit DRAM的电容器

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In order to realize 1 Gbit DRAMs, we have developed a 0.228 μm2 trench type cell. Two methods are employed to shrink thememory cell size. One is a “bottle shaped” capacitor, whichhas a larger diameter than the opening for the storage node. For thiscapacitor structure, we have verified 30% capacitance increase keepingthe trench opening, sufficiently high breakdown field of capacitordielectric, and less than 1/1000 of a soft-error rate compared with theconventional one. The other is a 6F2 cell layout suitable foran open-folded-bit-line architecture, which reduces to 75% for theconventional 8F2 cell layout with the same feature size, F.We have also confirmed that a P+ poly gate transistor has asufficient overlap tolerance (more than 0.1 μm) between the transfergate and the trench edge by using three-dimensional device simulator.These results strongly support feasibility of our novel cell
机译:为了实现1 Gbit DRAM,我们开发了0.228μm 2 沟槽式电池。有两种方法可以缩小 存储单元大小。一个是“瓶状”电容器, 直径大于存储节点的开口。为了这 电容器结构,我们已验证保持30%的电容增加 沟槽开口,足够高的电容器击穿场 介电质,与软错误率相比不到软错误率的1/1000 常规的。另一种是6F 2 单元布局,适用于 开放式折线结构,对于 具有相同特征尺寸F的常规8F 2 单元布局。 我们还证实了P + 多晶硅栅极晶体管具有 转印之间有足够的重叠公差(大于0.1μm) 栅和沟槽边缘通过使用三维设备模拟器来实现。 这些结果有力地支持了我们新型电池的可行性

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