Wafer level monitoring and process optimization for robust via EMreliability

摘要

Via electromigration (EM) lifetime correlates with the initial viaresistance. We have found that the single Kelvin via structure is moreeffective as a wafer-level reliability (WLR) monitor than the viachains. Using this monitor, we have optimized the via process for 0.35u/0.25 u applications