Optimization of novel oxide-free insulated gate structure for InPhaving an ultrathin silicon interface control layer

摘要

Attempts were made to clarify the cause for the poorreproducibility of successful processing accompanied with a low thetransconductance in the previous oxide-free InP MISFET having anultrathin Si interface control layer (Si ICL). A detailed in-situ XPSstudy made for each step of processing indicated that deficiency of P onthe InP surface took place by the irradiation of high energy Si beamduring the growth of Si ICL. Then, a modified passivation structurehaving an In_0.53Ga_0.47As cap layer was proposedand investigated. In-situ XPS study indicated that the novel gatestructure prevents desorption of P from the InP surface. In-situcontactless C-V method showed a low and wide interface state densitydistribution with a minimum of 2×1011 cm-2eV-1. A long-gate InP MISFET test device with a gate lengthof 2 μm exhibited a maximum g_m of 123 mS/mm and a highdrain current of 389 mA/mm