25 ps/gate GaAs standard cell LSIs using 0.5 μm gate MESFETs

摘要

A design system of GaAs standard cell LSIs using 0.5-μm MESFETsis presented. This design system is intended to be used to design LSIswhose operating speed is from several hundred MHz to several GHz. Abasic gate is DCFL (direct coupled FET logic), and the delay time isless than 25 ps. The library includes 40 cells and 8 I/O buffers whichare designed to be compatible with ECL 10 K, TTL (transistor-transistorlogic), CMOS, and GaAs. Using this design system, an LSI was fabricated,and its performance was evaluated. The results of the evaluation showthat the error in postlayout simulation is under 10%