Process-optimization for sub-30 ps BiCMOS technologies for mixedECL/CMOS applications

摘要

The authors present a 0.8 μm BiCMOS technology forhigh-performance digital applications. The underlying optimizationstrategy to trade off both bipolar vs. CMOS speed and cutoff-frequencyvs. collector-emitter breakdown voltage is described. Based on thisapproach 23.5 GHz cutoff frequency and 28 ps CML gate-delay times couldbe obtained for the bipolar device, making this technology perfectlysuited for mixed CMOS/ECL (emitter-coupled logic) types of applications.This is additionally proved by high-speed benchmark circuits such as 2:1frequency dividers operating up to 13.5 GHz