With electronic package tends to be lighter, thinner and smaller, the design of multi-chip become more and more popular. Howev'er, multi-chip in a package also represents multiple heat sources that will result in high thermal dissipation and new technology is required to remove the heat effectively. The 3D stacked package with Through Silicon Via (TSV) technology is developed for chip to chip stacking in a package with superior electrical performance and suspected worse thermal performance than conventional stacking die structures. In this study, we present the thermal characteristic for System in Package (SiP) with TSV technology using the Finite Different Modeling (FDM) method. The SiP package has a memory chip stacking on FPGA that aims to reduce the placement and routing areas on board. The evaluation topics covered impacts of TSV and dummy bumps, power consumption variations, die size and package size effects. The results indicate that the package with TSV can perform better thermal performance of about 7% thermal improvement compare to the package without TSV. Besides, the influences of the TSV structure designs and material property options on thermal performance are investigated in the study.
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