Including higher-order moments of RC interconnections inlayout-to-circuit extraction

摘要

This paper presents a reduction technique that transforms large RCnetworks into a minimal admittance network between the terminals, andthat at the same time preserves the moments of each admittance exactly,up to any desired order. Any RC network can be dealt with, includingcapacitive coupling between lines. The technique presented has beenincorporated in an efficient layout-to-circuit extractor using ascanline approach. The extracted moments can be used either incombination with Pade approximants for detailed timing-analysis, orsimple RC models can be obtained directly by fitting to the extractedmoments. The main advantage over AWE is that nodes are eliminated on thefly, thus reducing memory usage up to an order of magnitude