FPGA synthesis for minimum area, delay and power

摘要

In this paper, we address the problems of minimizing the area,delay and power during synthesis of field programmable gate arrays(FPGAs). We use Boolean decomposition techniques to minimize the numberof configurable logic blocks (CLBs), the depth of the network and thepower dissipations. We use OBDDs to represent functions so that ourmethods can be implemented more effectively. Our mapping algorithm isbased on function decomposition which was pioneered by Ashenhurst [1959]