FPGA high-level synthesis METHOD FOR OPTIMIZATION CIRCUIT BY USING HIGH-LEVEL SYNTHESIS OF FPGA

摘要

This disclosure is a method for optimizing the high-level synthesis results of an FPGA. The circuit optimization method includes analyzing a calculation process to be executed by a pipelining method, merging a plurality of unit operations belonging to a calculation process based on the analysis result into a single complex operation, and calculating the calculation process based on the merged result. And generating an optimized operation circuit and compiling based on the generated operation circuit.