Layout verification of VLSI circuits can be speeded upsignificantly by parallel execution. The approach described in thispaper combines parallel and hierarchical verification of cells and cellareas using geometrical partitioning. In contrast to earlier approaches,design rule check and netlist extraction are performed in parallelwithout any functional restriction. This is accomplished by a newconcept called multiple execution switching. Thus, industrial leadingedge VLSI circuits can be handled. High speedups are obtained for largereal-world layouts. A productive use is possible and will reducetime-to-market considerably
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