Packaging Technology and Design Challenge for Fine Pitch Micro-Bump Cu-Pillar and BOT (Direct Bond on Substrate-Trace) Using TCNCP (Thermal Compression with Non-Conductive Paste Underfill) Method

摘要

The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(ThermalCompression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is oneof the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (smallform factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chipsize (i.e. 100 mm~2) has been established and are in use for HVM production, there are several challenges to be addressed forfurther development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die largerthan 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust microjointreliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendationsbased on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology hasbeen used for the successful launching of the company FPGA products with SFF packaging technology.