【24h】

Electrical performance analysis of a three-dimensional package

机译:三维封装的电气性能分析

获取原文

摘要

Three-dimensional packaging is considered to offer a solution forhigh packaging density and enhanced electrical performance, which arerequired for the present and future electronic systems. A new type ofthree-dimensional package was recently developed. These were named“memory cubes”, in which thin small outline J-leadedpackages or thin quad flat J-leaded packages were stacked, andelectrically interconnected by soldering of the outer leads. Analyses ofelectrical performances of the memory cubes as the main memories in acomputer system were made through the electrical simulations of a 4Mb×9 DRAM memory cube and an equivalent 4 Mb×9 DRAM singleinline memory module. Electrical simulation showed that memory cubereduced the capacitance load of the longest on-board nets of typicalmemory board by 5% to 10%, reduced the reflection behavior of these netsby its lumped load character, and resulted in an overalldriver-to-receiver net performance improvement versus the equivalentsingle inline memory module by about 15%
机译:三维包装被认为可以为 高包装密度和增强的电气性能,这是 当前和将来的电子系统所需。一种新型的 最近开发了三维包装。这些被命名 “内存块”,其中细小的轮廓由J引线 封装或四方扁平J引线薄封装堆叠在一起,然后 通过外部引线的焊接实现电气互连。分析 存储立方体作为主存储器中的电气性能 计算机系统是通过对4 Mb×9 DRAM存储器立方体和等效的4 Mb×9 DRAM单个 嵌入式内存模块。电气仿真表明,存储立方体 降低了典型的最长车载网络的电容负载 内存板降低5%到10%,减少了这些网的反射行为 根据其集总负载特性,得出整体 驱动器到接收器的净性能相对于同类产品的提高 单列直插式内存模块约减少15%

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号