Cellular and reentrant layouts for semiconductor wafer fabricationfacilities

摘要

We study alternative facility layouts for semiconductor waferfabrication facilities using a process developed for manufacturing3-dimensional CMOS devices as a research vehicle. Simulation experimentsindicate that cellular layouts requiring only modestly higher capitalinvestment can yield significantly lower cycle times in heavily loadedfabs. These results suggest that the savings in operating costs such asinventory holding cost over the life of the process may render theadditional capital investment required by the cellular layoutseconomically justifiable