The ability to align and bond with precision, one micron or less,two silicon wafers or a silicon wafer to another substrate is becoming acritical issue for a variety of semiconductor applications. For CMOSdevices this technology will be applied for chip-scale packaging andalso for advanced 3-D interconnect processes. In themicroelectromechanical systems (MEMS) arena, accurate alignment of twosilicon micromachined wafers enables the design of more advanced MEMSdevices and aggressive die shrinks of existing products. In this paperwe discuss the advantages and disadvantages of varioussubstrate-to-substrate alignment techniques including infrared, throughwafer via, inter-substrate optical and wafer backside alignment methods.We also report on a new approach to wafer-to-wafer alignment that relieson precision alignment positioning systems to register and align waferswith one micron or better precision. Test results from thiswafer-to-wafer alignment system demonstrate that one micron alignmentaccuracy can be routinely obtained. This new wafer-level alignment andbonding technique is particularly well suited for high-volumemanufacturing due to the long-term stability of the precision alignmentpositioning system. This paper gives a brief overview of some typicaluses of aligned wafer-level bonding for chip-scale, 3-D interconnect andMEMS applications
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