Verification of SDRAM controller using SystemVerilog

摘要

Synchronous DRAM (SDRAM) has become memory of choice for desktop computers, laptops and embedded systems due to its significant features like high speed, burst access..etc. As SDRAM has many phases of operation like write phase, burst phase, active phase, precharge phase there is need for a memory controller to manage the memory. The main purpose of the SDRAM controller is to refresh the SDRAM cells periodically and control the flow of data to/from SDRAM. Efficient design and verification of the SDRAM controller is required to minimize the memory access latency and ensure the correct operation of SDRAM. In this paper we have verified the SDRAM controller using SystemVerilog test bench architecture. Our model has verified the SDRAM controller against most of the test cases provided by the specification sheet and also achieved 100 percent code coverage. The design was verified using Modelsim SE-64 10.5.