From Wafer Processing To Advanced Packaging: Broadening The Applications For Tsv’S Beyond The High End

摘要

Electronics packaging technology has been in a period of rapid technology advancement for a number of years, as the package takes on a larger role in improving the cost and performance of systems, such as laptops, tablets and smart phones. This trend will only increase with the introduction of 5G networks, the rising electronics content of automobiles, and the general proliferation of connected systems. The challenges for packaging include handling a greater density of interconnections, connecting multiple chips in the same package and managing greater heat loads by mitigating the stresses they create. The higher frequencies associated with 5G will require new structures and fabrication techniques to minimize signal delays and losses, especially between chips within a package. The smaller interconnect features and tighter specifications blur the boundary between wafer processing and packaging: many of the processes that were historically part of the fab line are finding their way into the packaging process. However, the materials, structures and specifications are very different, and this presents both a challenge and an opportunity. The players who find creative applications for wafer fabrication processes will differentiate themselves from the competition and win market share. We will focus here on a selection of new features for Cu plating in advanced packaging, and which pose special challenges to the process. Some of them, such as embedded conductor for RDL and large via fill plus pad, require a variation of the preferential “bottom up” Cu deposition used in damascene and TSV (Through Silicon Via) processes. We will discuss how the plating chemistry and process is adapted to create these new features in an advanced packaging process flow.