FPGA Design and Implementation of Accelerated Stereo Matching for Obstacle Detection

摘要

This paper present hardware architecture of low-complexity stereo matching and its implementation. The AD-CENSUS stereo matching algorithm is modified for hardware design and implemented in Xilinx Kintex UltraScale KU040 board. Furthermore the calibration and rectification for stereo camera is included in design. It is accelerated with low hardware resources, and can be obtained the reliable quality of disparity map for obstacle detection.