Overview of Co-design Considerations for ESD Protection in System-in-Packages (SiPs)

摘要

System in Package (SiP) solutions are increasing attractive for the evolution of the Moore's Law, and the ESD threats are still existed for the integration and application procedures. The SiPs combine several active dies with different processes and passive components into a single package to promote the minimization, high performance and easy to use capability. The co-design methodologies of on-chip and off-chip are discussed and overviewed briefly in this paper for ESD robustness improvement.