6.4 A 0.5-to-2.5GHz Multi-Output Fractional Frequency Synthesizer with 90fs Jitter and -106dBc Spurious Tones Based on Digital Spur Cancellation

摘要

There is need for a low-power, compact, means of generating multiple, low-jitter, spectrally pure, clock signals at different frequencies using a single reference oscillator, both in wireline and wireless applications, owing to circuit size, cost, and complexity considerations. PLL-based frequency synthesis - analog or digital - can achieve very low jitter and spur levels, but the VCO size and/or power consumption concerns preclude its duplication for multiple on-chip clock generators [1,2]. Open-loop digital methods based on digital-to-phase or digital-to-time converters (DPCs) are compact and employ no power-hungry oscillators, but their circuit errors and mismatches result in strong spurious tones.